As semiconductor devices become more integrated, the size of the gate electrode and active region decreases and sheet resistivity increases. Consequently, the performance of the semiconductor devices incorporating these structures becomes increasingly deteriorated. Although a silicide is typically formed on the gate electrode and active region, the diminution of the gate electrode and active region prevents the formation of a stable silicide.
One of the methods to solve the above-mentioned problems is to enlarge the surface area of the gate electrode by over-etching spacers during an etching process.
FIG. 1a through FIG. 1f are cross-sectional views illustrating a conventional method of fabricating a gate electrode. Referring to FIG. 1a, a gate oxide layer (not shown) and a gate electrode 101 are formed on a semiconductor substrate 100. A first insulating layer is deposited on the substrate 100 and on the gate electrode 101. A second insulating layer is then deposited on the first insulating layer. First spacers 102 and second spacers 103 are formed on the sidewalls of the gate electrode 101 by etching the entire area of the substrate without an etching mask.
Referring to FIG. 1b, the end portion of the first and second spacers 102, 103 may be partially exposed by over-etching the entire area of the substrate without an etching mask to fabricate more stable silicide in preparation for later processes. A cleaning process is then performed to remove a residual oxide layer 104 on the active region and the gate electrode. In addition, the residual oxides 104 on the first and second spacers 102, 103 are also removed. As a result, metallic materials deposited on the gate electrode 101 and the substrate 100 will readily react with the gate electrode and the substrate 100 during a later silicide formation process.
Referring to FIG. 1c, during the cleaning process, the first spacers 102 are etched deeper than the second spacers 103 and the gate electrode 101 so that voids A are formed between the second spacers 103 and the gate electrode 101.
Referring to FIG. 1d, highly concentrated N or P type impurity ions are implanted into the entire area of the resulting substrate 100 in order to form a source and a drain junction 105.
Referring to FIG. 1e, Ti 106 is deposited on the resulting substrate for silicide.
Referring to FIG. 1f, an annealing process is then performed to cause a reaction between the Silicide layer and the structure including the gate electrode 101 and the source/drain junction 105. A Ti silicide layer 108 is then formed on the gate electrode 101, but not on the first and second spacers 102, 103. A cleaning process to remove the unreacted Ti is then performed to complete the illustrated prior art silicide formation process.
Wu, U.S. Pat. No. 6,534,405, describes a method for fabricating a MOSFET device using a dual salicide formation procedure.
Lee et al., U.S. Pat. No. 6,383,882, describes a method for fabricating a MOS transistor using a selective silicide process wherein a gate insulating layer and a gate poly-silicon layer are sequentially formed on a silicon substrate, and a gate spacer is formed on a side wall of the gate insulating layer and the gate poly-silicon layer.
However, the above-mentioned prior art methods for fabricating a silicide of a semiconductor device have the following problems.
First, during the cleaning process of the residual oxide layer 104 on top of the active region and the gate electrode 101, the first spacers 102 are etched deeper than the second spacers 103 and the gate electrode 101. Voids A are then formed between the second spacer 103 and the gate electrode 101. The voids A can decrease the reliability of the semiconductor device.
Second, the gate oxide layer in the active region may be simultaneously removed during over-etching. Thus, the desired thickness of the oxide layer cannot be obtained.